Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a damascene bit line and a method for manufacturing the same.
As an integration degree of a semiconductor device is rapidly increased, the size of a semiconductor device channel length is gradually decreased. Accordingly, it is more difficult to guarantee a sufficient sensing margin for operation of the semiconductor device. The most important factor in guaranteeing the sensing margin is as follows. As the semiconductor device is reduced in size, a storage electrode is reduced in size, so that it is difficult to guarantee capacity of the storage electrode. In addition, it is also difficult to reduce the parasitic capacitance of a bit line to a desired level. This substantially affects the sensing margin. This parasitic capacitance is decided by various factors, for example, permittivity of an insulator formed between conductors, a facing area of the conductors, and a distance between the conductors. The distance between the conductors is gradually shortened, such that it is difficult to reduce the parasitic capacitance to a desired level. In order to overcome this problem, a method for reducing the size of a bit line or the size of a storage electrode contact has been introduced, but the aforementioned method increases the cell resistance.
As described above, as the integration degree of the semiconductor device is rapidly increased, the difficulty of forming a hole-type storage electrode contact in a cell array is also increased. As a result, instead of using the conventional method for forming the bit line and then forming the hole-type storage electrode contact, there has been proposed a new method in which a line-type storage electrode contact is formed and a bit line is formed by a damascene technique, so that the line-type storage electrode contact can be separated from the bit line.
However, the above-mentioned method for forming the bit line using the above-mentioned damascene technique has a disadvantage in that the bit line is formed closer to the storage electrode contact. In addition, a titanium nitride (TiN) film is formed over the sidewalls of the bit line as well as at the bottom of the bit line, resulting in increased parasitic capacitance.